1. Field of the Invention
The present invention relates to a process for the preparation of a thin film transistor and more particularly, to a fabrication process of a thin film transistor that reduces the fabrication steps, saves manufacturing costs, and enhances the operating property, durability and the interface property.
2. Description of the Related Art
Several thin film transistors (hereinafter TFT) are well known in the art. One such conventional TFT is shown in FIG. 1. Such a conventional TFT, as shown in FIG. 1, includes a laminated structure in which a gate electrode of Cr on a glass substrate, a gate insulating layer of SiN, an amorphous silicon layer 4, an etch stopper layer of SiN, an n+ amorphous silicon layer 3 doped with impurities, and an aluminum layer 5 used as a drain electrode and a source electrode laminated sequentially.
As shown in FIGS. 2(a) to 2(g), a process for the preparation of the conventional TFT discussed above includes the steps of depositing and patterning a gate layer of Cr on a glass substrate to provide a gate electrode (FIG. 2(a)); depositing sequentially a gate insulating layer of SiN, an amorphous silicon layer 4 as a semiconductor and an etch stopper layer of SiN over the gate electrode (FIG. 2(b)); patterning the etch stopper layer of SiN to provide an etch stopper layer (FIG. 2(c)); depositing an n+ amorphous silicon layer 3 (FIG. 2(d)); patterning the n+ amorphous silicon layer 3 and the amorphous silicon layer 4 (FIG. 2 (e)); depositing and patterning the aluminum layer 5 to provide source and drain electrodes (FIG. 2(f)); and etching the n+ amorphous silicon layer by an RIE (Reactive Ion Etching) Process (FIG. 2 (g)).
However, because such a conventional TFT preparation process uses the RIE process, it is very difficult to control the etching depth of the n+ amorphous silicon layer 3 when the n+ amorphous silicon layer 3 is etched by the RIE process. Therefore, in the case where the n+ amorphous silicon layer 3 is etched by the RIE process, most careful attention is required in order not to etch the amorphous silicon layer together with the n+ amorphous silicon layer. It is why the conventional TFT does need an etch stopper layer between the amorphous silicon layer and the n+ amorphous silicon layer to prevent the amorphous silicon layer from being etched together with the n+ amorphous silicon layer.
Also, the interface property between the n+ amorphous silicon layer and the amorphous silicon layer could be deteriorated because the steps of depositing and patterning the etch stopper layer has to be performed before the step of depositing the n+ amorphous silicon layer.
The deterioration of the interface property between the n+ amorphous silicon layer and the amorphous silicon layer are caused by the following reasons:
1) an exposure to the atmosphere could easily oxidize the n+ amorphous silicon layer on its exposed surface, which results in deterioration in property;
2) the patterning of the etch stopper layer of SiN by etching could affect the surface of the amorphous silicon layer.
Accordingly, as described above, the conventional preparation steps are complicated and difficult because additional steps for depositing and patterning the etch stopper layer of SiN are required. Also, the interface property between the n+ amorphous silicon layer and the amorphous silicon layer is deteriorated because the sequential depositions of the n+ amorphous silicon layer on the amorphous silicon layer cannot be carried out by adding the depositing and patterning steps of the etch stopper layer of SiN.